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a61l6316 series 64k x 16 bit high speed cmos sram (may, 2001, version 1.0) amic technology, inc. document title 64k x 16 bit high speed cmos sram revision history rev. no. history issue date remark 0.0 initial issue july 14, 2000 preliminary 1.0 final spec. release may 8, 2001 final add - 10 spec. change i cc1 from 120ma to 220ma ( - 12) ch ange i cc1 from 100ma to 210ma ( - 15) change i sb1 from 8ma to 12ma change i cdr from 1ma to 5ma add t be , t blz , t bhz , t bw parameters
a61l6316 series 64k x 16 bit high speed cmos sram (may, 2001, version 1.0) 1 amic technology, inc. features n center power pinout n supply voltage: - 10: 3.3v+10%, - 5% - 12, - 15: 3.3v 10% n access times: 10/12 /15 ns (max.) n current: operating: - 10: 230ma (max) - 12: 220ma (max.) - 15: 210ma (max.) standby: ttl: 25ma (max.) cmos: 12ma (max.) n full static operation, no clock or refreshing required n all inputs and outputs are directly ttl - compatible n common i/o using three - state output n data retention voltage: 2v (min.) n available in 44 - pin 400mil soj and 44 - pin 400mil tsop(ii) forward packages. general description the a61l6316 is a high speed 1,048,576 - bit static random access memory organized a s 65,536 words by 16 bits and operates on low power supply voltage from 3.0v to 3.6v. it is built using amic?s high performance cmos process. inputs and three - state outputs are ttl compatible and allow for direct interfacing with common system bus structur es. the chip enable input is provided for power - down, to disable the device. two byte enable inputs and an output enable input are included for easy interfacing. data retention is guaranteed at a power supply voltage as low as 2v. pin configuration n soj / tsop(ii) 1 a0 a1 a2 a3 a4 ce i/o 0 i/o 1 i/o 2 i/o 3 vcc gnd i/o 4 i/o 5 i/o 6 i/o 7 23 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a15 a14 a13 oe hb lb i/o 15 i/o 14 i/o 13 i/o 12 vcc gnd i/o 11 i/o 10 i/o 9 i/o 8 a61l6316s(v) 17 18 19 20 21 22 24 25 26 27 28 29 we a5 a6 a7 a8 nc nc a12 a11 a10 a9 nc
a61l6316 series (may, 2001, version 1.0) 2 amic technology, inc. block diagram decoder 1,048,576-bit memory array column i/o input data circuit control circuit vcc gnd i/o 7 i/o 0 a15 a14 a0 we hb input data circuit i/o 8 i/o 15 ce lb oe
a61l6316 series (may, 2001, version 1.0) 3 amic technology, inc. pin description - soj/tsop(ii) pin no. symbol description 1 - 5, 18 - 21, 24 - 27,42 - 44 a0 - a15 address inputs 6 ce chip enable input 7 - 10, 13 - 16, 29 - 32, 35 - 38 i/o 0 - i/o 15 data input/outputs 17 we write enable input 39 lb byte enable input (i/o 0 to i/o 7 ) 40 hb byte enable input (i/o 8 to i/o 15 ) 41 oe output enable input 11, 33 vcc power 12, 34 gnd ground 22 , 23, 28 nc no connection recommended dc operating conditions (t a = 0 c to + 70 c) symbol parameter min. typ. max. unit *vcc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input h igh voltage 2.2 - vcc + 0.3 v v il input low voltage - 0.3 - 0.8 v c l output load - - 30 pf * - 10 v cc min : 3.135v
a61l6316 series (may, 2001, version 1.0) 4 amic technology, inc. absolute maximum ratings* vcc to gnd . . . . . . . . . . . . . . . . . . . . . . - 0.5v to +4.6v in, in/out volt to gnd . . . . . . . . - 0.5v to vcc + 0.5v operating temperature, topr . . . . . . . . . . 0 c to +70 c storage temperature, tstg . . . . . . . . . - 55 c to +125 c power dissipation, p t . . . . . . . . . . . . . . . . . . . . . 0.7w soldering temp. & time . . . . . . . . . . . . . 260 c, 10 sec *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those in dicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (t a = 0 c to + 70 c, - 10: 3.3v+1 0%, - 5%; - 12, - 15: 3.3v 10%) symbol parameter a61l6316 - 10 a61l6316 - 12 a61l6316 - 15 unit conditions min. max. min. max. min. max. ? i li ? input leakage - 2 - 2 - 2 m a v in = gnd to vcc ? i lo ? output leakage - 2 - 2 - 2 m a ce = v ih , oe = v ih v i/o = gnd to vcc i cc1 (2) dynamic operating current - 230 - 220 - 210 ma ce = v il , i i/o = 0 ma min. cycle, duty = 100% i sb - 25 - 25 - 25 ma ce = v ih i sb1 standby power supply current - 12 - 12 - 12 ma ce 3 vcc - 0.2v, v in 3 vcc - 0.2v or v in 0.2v v ol output low voltage - 0.4 - 0.4 - 0.4 v i ol = 8 ma v oh output high voltage 2.4 - 2.4 - 2.4 - v i oh = - 4 ma notes: 1. v il = - 3.0v for pulses less than 20 ns. 2. i cc1 is dependent on output loading, cycle rates, and read/write patterns.
a61l6316 series (m ay, 2001, version 1.0) 5 amic technology, inc. truth table ce oe we lb hb i/o 0 to i/o 7 mode i/o 8 to i/o 15 mode vcc current h x x x x not selected not selected i sb1 , i sb l l read read i cc1 , i cc2 , i cc l l h l h read high - z i cc1 , i cc2 , i cc h l high - z read i c c1 , i cc2 , i cc l l write write i cc1 , i cc2 , i cc l x l l h write not write/hi - z i cc1 , i cc2 , i cc h l not write/hi - z write i cc1 , i cc2 , i cc l x high - z high - z i cc1 , i cc2 , i cc l h h x l high - z high - z i cc1 , i cc2 , i cc x x x h h not selec ted not selected i sb1 , i sb note: x = h or l capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance - 6 pf v in = 0v c i/o * input/output capacitance - 8 pf v i/o = 0v * these parameters are sampled and not 1 00% tested.
a61l6316 series (m ay, 2001, version 1.0) 6 amic technology, inc. ac characteristics (t a = 0 c to +70 c, - 10: 3.3v+10%, - 5%; - 12, - 15: 3.3v 10%) symbol parameter a61l6316 - 10 a61l6316 - 12 a61l6316 - 15 unit min. max. min. max. min. max. read cycle t rc read cycle time 10 - 12 - 15 - ns t aa address a ccess time - 10 - 12 - 15 ns t ace chip enable access time - 10 - 12 - 15 ns t be byte enable access time - 5 - 6 - 8 ns t oe output enable to output valid - 5 - 6 - 8 ns t clz chip enable to output in low z 3 - 3 - 3 - ns t olz output enable to output in low z 0 - 0 - 0 - ns t blz byte enable to output in low z 0 - 0 - 0 - ns t chz chip disable output in high z 0 5 0 6 - 8 ns t bhz byte disable to output in high z 0 5 0 6 0 8 ns t ohz output disable to output in high z 0 5 0 6 0 8 ns t oh output hold from address change 3 - 3 - 3 - ns write cycle t wc write cycle time 10 - 12 - 15 - ns t cw chip enable to end of write 8 - 10 - 12 - ns t bw byte enable to end of write 8 - 10 - 12 - ns t as address setup time of write 0 - 0 - 0 - ns t aw address valid to end of write 8 - 10 - 12 - ns t wp write pulse width 8 - 10 - 12 - ns t wr write recovery time 0 - 0 - 0 - ns t whz write to output in high z 0 5 0 6 0 8 ns t dw data to write time overlap 5 - 6 - 7 - ns t dh data hold from write time 0 - 0 - 0 - ns t ow output active from end of write 3 - 3 - 3 - ns notes: t chz , t bhz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
a61l6316 series (m ay, 2001, version 1.0) 7 amic technology, inc. timing waveforms read cycle 1 (1, 2, 4) t rc t oh t aa t oh address d out read cycle 2 (1, 2, 3) t rc t aa address t ace t chz 5 ce hb, lb t bhz 5 oe t clz 5 t be t blz 5 t oe t olz 5 t ohz 5 d out notes: 1. we is high for read cycle. 2. device is continuously enabled ce = v il , hb = v ih and, or lb = v il . 3. address valid prior to or coincident with ce and ( hb and, or lb ) transition low. 4. oe = v il . 5. transition is measured 200mv from st eady state. this parameter is sampled and not 100% tested.
a61l6316 series (m ay, 2001, version 1.0) 8 amic technology, inc. timing waveforms (continued) write cycle 1 (write enable controlled) t wc t aw address data in data out we hb, lb ce t wr 3 t cw t bw t as 1 t wp 2 t dw t dh t ow t whz 4
a61l6316 series (m ay, 2001, version 1.0) 9 amic technology, inc. timing waveforms (continued) write cycle 2 (chip enable controlled) t wc t aw address data in data out we hb, lb ce t wr 3 t cw 2 t bw t as 1 t wp t dw t dh t ow t whz 4
a61l6316 series (m ay, 2001, version 1.0) 10 amic technology, inc. timing waveforms (continued) write cycle 3 (byte enable controlled) t wc t aw address data in data out we hb, lb ce t wr 3 t cw t bw 2 t as 1 t wp t dw t dh t ow t whz 4 notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap (t wp , t bw ) of a low ce , we and ( hb and, or lb ). 3. t wr is measured from the earliest of ce or we or ( hb and, or lb ) going high to the end of the write cycle. 4. oe level is high or low. 5. transition is measured 200mv from steady state. this parameter is sampled and not 100% tested.
a61l6316 series (m ay, 2001, version 1.0) 11 amic technology, inc. ac test conditions input pulse levels 0v to 3.0v input rise and fall time 3 ns input and output timing reference levels 1.5 v output load see figures 1 and 2 +3.3v i/o 351 w 317 w 5pf* * including scope and jig. z o =50 w output r l =50 w v t =1.5v figure 1. output load figure 2. output load for t clz , t olz , t chz , t ohz , t whz , and t ow data retention characteristics (t a = 0 c to 70 c) symbol parameter min. max. unit conditions v dr vcc for data retention 2 3.6 v ce 3 vcc - 0.2v i ccdr data retention current - 5 ma vcc = 2.0v ce 3 vcc - 0.2v v in 3 vcc - 0.2v or v in 0.2v t cdr chip disable to data retention time 0 - ns see retention waveform t r operation recovery time t rc * - ms t rc = read cycle time
a61l6316 series (m ay, 2001, version 1.0) 12 amic technology, inc. low vcc data retention waveform vcc ce t cdr v ih 3.0v t r v ih 3.0v data retention mode v dr 3 2v ce 3 v dr - 0.2v t vr ordering information part no. access time (ns) op erating current max. (ma) standby current max. (ma) package a61l6316s - 10 44l soj a61l6316v - 10 10 230 12 44l tsop(ii) a61l6316s - 12 44l soj a61l6316v - 12 12 220 12 44l tsop(ii) a61l6316s - 15 44l soj a61l6316v - 15 15 210 12 44l tsop(ii)
a61l6316 series (m ay, 2001, version 1.0) 13 amic technology, inc. package information soj 44l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom max min nom max a 0.128 0.138 0.148 3.25 3.51 3.76 a 1 0.082 - - 2.08 - - a 2 0.105 0.110 0.115 2.67 2.79 2.92 b 0.015 - 0.020 0.38 - 0 .51 b 1 0.026 0.028 0.032 0.66 0.71 0.81 c 0.007 - 0.013 0.18 - 0.21 d 1.120 1.125 1.130 28.45 28.58 28.70 e 0.435 0.440 0.445 11.05 11.18 11.30 e 1 0.394 0.400 0.405 10.01 10.16 10.29 e 2 0.370 bsc 9.40 bsc e 0.050 bsc 1.27 bsc r 1 0.030 0.035 0.040 0.76 0.89 1.02 q 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. b b 1 d y 0.004 a 2 a a 1 y e r 1 c e 2 q e e 1 seating plane d 44 23 22 1 min 0.025"
a61l6316 series (m ay, 2001, version 1.0) 14 amic technology, inc. package information tsop 44l ( type ii) outline dimensions unit: inches/mm 1 e l 1 l 1 c 44 zd d y e d b l l q a 1 a 2 a e 1 dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.012 - 0.018 0.30 - 0.45 c 0.005 - 0.008 0.12 - 0.21 d 0.720 0.725 0.730 18.28 18.41 18.54 zd 0.032 ref 0.805 ref e 0.455 0.463 0.471 11.56 11.76 11.96 e 1 0.395 0.400 0.405 10.03 10.16 10.29 l 0.019 0.023 0.027 0.49 0.59 0.69 l 1 0.031 ref 0.80 ref e 0.031 bsc 0.80 b sc y - - 0.004 - - 0.10 q 0 - 5 0 - 5 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension zd includes end flash.

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